• DocumentCode
    1713745
  • Title

    An empirical study on the effects of physical design in high-level synthesis

  • Author

    Jha, Pradip K. ; Ramachandran, Champaka ; Dutt, Nikil D. ; Kurdahi, Fadi J.

  • Author_Institution
    Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
  • fYear
    1994
  • Firstpage
    11
  • Lastpage
    16
  • Abstract
    The authors explore the combined effect of style and aspect ratio variations on the area and delay of RT level components, which in turn affects high-level synthesis decisions. Their results indicate that point models, where a component´s area and delay are assumed to be constant for a given style, are inadequate for use in the synthesis process due to the large variations in the area and delay that occur when component aspect ratios are varied. They believe that the results have some deep implications with respect to the flow of the design tasks during high level synthesis
  • Keywords
    logic CAD; shift registers; RT level components; aspect ratio; component area; component delay; high-level synthesis; physical design; point models; register transfer design; style; Algorithm design and analysis; Area measurement; Contracts; Costs; Delay effects; High level synthesis; Logic design; Scheduling algorithm; Very large scale integration; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 1994., Proceedings of the Seventh International Conference on
  • Conference_Location
    Calcutta
  • ISSN
    1063-9667
  • Print_ISBN
    0-8186-4990-9
  • Type

    conf

  • DOI
    10.1109/ICVD.1994.282638
  • Filename
    282638