Performance evaluation of CMOS ring-oscillators with source/drain regions fabricated by asymmetric/symmetric ion-implantation

Author

Ohzone, T. ; Miyakawa, Tetsu ; Matsuda, Toshihiro ; Yabu, Toshiki ; Odanaka, Shinji

Author_Institution

Dept. of Electron. & Inf., Toyama Prefectural Univ., Japan

fYear

1997

Firstpage

131

Lastpage

136

Abstract

0.5 μm CMOS ring-oscillators with LDD-type surface-channel n-MOSFETs and EPS-type buried-channel p-MOSFETs with asymmetric/symmetric source/drain fabricated by four kinds of ion-implantation methods were measured for evaluating the circuit performance. The ion-implantation methods were correlated to supply-current/oscillation-frequency/delay-power product and substrate current of the ring-oscillator. The most preferable implantation method was the symmetric 7°×4-implantation in terms of circuit performance, asymmetry/mismatch and punchthrough immunity of CMOSFET

Keywords

CMOS analogue integrated circuits; integrated circuit technology; ion implantation; oscillators; 0.5 micron; CMOS ring oscillator; CMOSFET circuit performance; EPS-type buried-channel p-MOSFET; LDD-type surface-channel n-MOSFET; asymmetric ion implantation; fabrication; mismatch; punchthrough immunity; source/drain region; substrate current; supply-current/oscillation-frequency/delay-power product; symmetric ion implantation; CMOSFETs; Circuit optimization; Degradation; Electric variables; Electrodes; Fabrication; Impurities; Large scale integration; MOSFET circuits; Shadow mapping;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1997. ICMTS 1997. Proceedings. IEEE International Conference on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-3243-1

Type

conf

DOI

10.1109/ICMTS.1997.589356

Filename

589356