Ultra fine-grain template-driven synthesis

Discusses an alternate strategy for data-path synthesis. In this approach a Very Long Instruction Word (VLIW) processor structure consisting of a consolidated register file interconnected with functional units is used as the underlying architecture. The functional units are described using ultra fine-grain templates which detail the functionality at the component level. During scheduling the architectural organization of the VLIW is relaxed, allowing a Percolation-based Scheduler to modify the templates so that parallelism in the application dictates architectural modification. The experiments demonstrate performance improvements on standard benchmarks, as well as improved memory port utilization for the synthesized VLIW architectures