CM-SIM: a parallel circuit simulator on a distributed memory multiprocessor

We took the design of on existing circuit simulator, SPICE, considered various parallelization techniques, and selected a relaxation-based algorithm, Iterated Timing Analysis, for further study. In this report, the implementation of this algorithm on the CM-5 is described. Simulation is performed by a collection of subcircuits communicating with one another by sending asynchronous event messages. Initial studies on two platforms, Split-C, a parallel extension of C, and the CMMD message passing library, indicate that this approach, with appropriate partitioning and scheduling taking granularity into account, has a great deal of potential for reducing the cost of circuit simulation. We also tried to exploit parallelism by scheduling the events optimistically. Trace driven analysis shows that the optimistic simulation method exploits more parallelism than the conservative methods for circuits with feedback signal paths