• DocumentCode
    1713911
  • Title

    A236 parallel DSP chip provides real-time video processing economically and efficiently

  • Author

    Morton, Steven G.

  • Author_Institution
    Oxford Comput. Inc., Oxford, CT, USA
  • fYear
    1996
  • Firstpage
    261
  • Lastpage
    268
  • Abstract
    Oxford Computer´s A236 parallel digital signal processor chip is flexible, fully programmable and designed to compactly and inexpensively provide live video capture, processing and display. The use of single-chip, parallel processing with integrated data and instruction caches, and an inexpensive, high performance memory system, provide high performance at low cost. An extended, single-instruction multiple-data (SIMD) architecture with one, 24-bit scalar processor and four, 16-bit vector processors, is used. Five instructions are issued each clock cycle with a 40 MHz clock, providing up to 200 MIPS. Two, 16-bit, bi-directional, double-buffered, DMA ports support simultaneous video acquisition and display, and interface directly to common video decoder and encoder chips with no glue logic. A minimum system that provides all input and output frame buffering contains only three chips, an A236 Chip, a 32-bit wide, synchronous DRAM, and a serial I2C EEPROM, plus analog video interface chips. A full set of software development tools that runs under MS Windows is available free, including an enhanced C-compiler that provides a simple method for representing parallel operations on data structures. An evaluation kit containing the software tools and the A236 Video Processing System I is also available
  • Keywords
    digital signal processing chips; image processing; parallel processing; real-time systems; software tools; video coding; 16 bit; 24 bit; 32 bit; 40 MHz; A236 Video Processing System I; A236 parallel DSP chip; C-compiler; DRAM; MS Windows; Oxford Computer; analog video interface chips; common video decoder; encoder chips; high performance memory system; instruction caches; live video capture; output frame buffering; real-time video processing; serial I2C EEPROM; single-instruction multiple-data architecture; software development tools; video acquisition; Bidirectional control; Clocks; Computer displays; Concurrent computing; Costs; Digital signal processing chips; Digital signal processors; Parallel processing; Signal design; Vector processors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ELECTRO '96. Professional Program. Proceedings.
  • Conference_Location
    Somerset, NJ
  • Print_ISBN
    0-7803-3271-7
  • Type

    conf

  • DOI
    10.1109/ELECTR.1996.501237
  • Filename
    501237