DocumentCode :
1714110
Title :
The Future of Nanometer SOC Design
Author :
Leibson, Steve
Author_Institution :
Tensilica, Inc., Santa Clara, CA
fYear :
2006
Firstpage :
1
Lastpage :
6
Abstract :
Moore´s law (double the number of transistors at each new processing node) and classical semiconductor scaling (faster transistors running at lower power at each new processing node) parted company after the 130nm processing node. As a result, on-chip clock rates have stopped rising as fast and transistor power levels have stopped falling as quickly as they did in the past. This change in the trend demands a change to a system-design style that emphasizes the use of multiple processor cores (Leibson, 2006)
Keywords :
integrated circuit design; multiprocessing systems; nanoelectronics; system-on-chip; multiple processor cores; nanometer SOC design; system-design style; Clocks; Control systems; Large scale integration; Lithography; Logic design; Microprocessors; Moore´s Law; Printed circuits; Read only memory; Read-write memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
System-on-Chip, 2006. International Symposium on
Conference_Location :
Tampere
Print_ISBN :
1-4244-0621-8
Electronic_ISBN :
1-4244-0622-6
Type :
conf
DOI :
10.1109/ISSOC.2006.321999
Filename :
4116440
Link To Document :
بازگشت