Implementation of an HSDPA Receiver with a Customized Vector Processor

Author

Rounioja, Kim ; Puusaari, Kimmo

Author_Institution

Nokia, Oulu

fYear

2006

Firstpage

1

Lastpage

4

Abstract

SIMD paradigm enhances cost and power efficiency of instruction set processors when the executed workload contains appropriate data level parallelism. In this paper, we investigate development of a SIMD ASIP for an HSDPA equalizer receiver for mobile handsets. The ASIP is based on a vector processor template with C-based programming interface. The template is enhanced to capture the 14.4Mbps HSDPA equalizer receiver functionality of the wireless modem. The solution provides improved flexibility compared to the conventional approach while requiring only modest design effort. The template and the design approach can be utilized also for other subsets of modem baseband

Keywords

equalisers; microprocessor chips; mobile handsets; modems; radio receivers; 14.4 Mbit/s; C-based programming interface; HSDPA receiver; SIMD ASIP; customized vector processor; equalizer receiver; mobile handsets; vector processor template; wireless modem; Application specific processors; Baseband; Computer architecture; Costs; Hardware; Modems; Multiaccess communication; Registers; Signal processing; Vector processors;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip, 2006. International Symposium on

Conference_Location

Tampere

Print_ISBN

1-4244-0621-8

Electronic_ISBN

1-4244-0622-6

Type

conf

DOI

10.1109/ISSOC.2006.322004

Filename

4116445