Simulated annealing for target-oriented partial scan

Author

Ravikumar, C.P. ; Rasheed, H.

Author_Institution

Dept. of Electr. Eng., Indian Inst. of Technol., New Delhi, India

fYear

1994

Firstpage

107

Lastpage

112

Abstract

In this paper, we describe algorithms based on simulated annealing for selecting a subset of flip-flops to be connected into a scan path. The objective for selection is to maximise the coverage of faults that are aborted by a sequential fault simulator. We pose the problem as a combinatorial optimization, and present a heuristic algorithm based on simulated annealing. The SCOAP testability measure is employed to assess the selection of flip-flops during the course of optimization. Our algorithms form a part of an integrated design package, TOPS, which has been designed as an enhancement to the OASIS standard-cell design automation system available from MCNC. We discuss the TOPS package and its performance on a number of ISCAS´89 benchmarks. We also present a comparative evaluation of the benchmark results

Keywords

combinatorial mathematics; flip-flops; logic CAD; logic testing; sequential circuits; simulated annealing; OASIS standard-cell design automation system; SCOAP testability measure; TOPS; combinatorial optimization; fault coverage maximisation; flip-flop subset selection; heuristic algorithm; integrated design package; profit function; scan path; sequential fault simulator; simulated annealing; target-oriented partial scan; Algorithm design and analysis; Benchmark testing; Circuit faults; Circuit testing; Flip-flops; Heuristic algorithms; Integrated circuit packaging; Integrated circuit testing; Shift registers; Simulated annealing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1994., Proceedings of the Seventh International Conference on

Conference_Location

Calcutta

ISSN

1063-9667

Print_ISBN

0-8186-4990-9

Type

conf

DOI

10.1109/ICVD.1994.282666

Filename

282666