Title :
Efficient Link Architecture for On-Chip Serial links and Networks
Author :
Balachandran, J. ; Kuijk, M. ; Brebels, S. ; Carchon, G. ; De Raedt, W. ; Nauwelaers, B. ; Beyne, E.
Author_Institution :
Microwave & RF Syst. Group, IMEC, Leuven
Abstract :
Serial links are an effective solution to address the growing on-chip communication bottlenecks in nano-CMOS technologies. This paper proposes efficient link architecture for on-chip serial links and networks. The proposed solution consists of a pre-emphasized differential driver and receiver interconnected by LC transmission lines. The LC transmission lines are implemented in packaging layers post processed directly above a standard CMOS wafer. The link enables simple register-to-register style data transfer, well suited for on-chip IO. The proposed scheme can offer data rates as high as 12.5 Gbps per channel for less than 0.5pJ of energy per bit on the 0.13mum technology
Keywords :
CMOS integrated circuits; integrated circuit interconnections; nanoelectronics; transmission lines; 0.13 micron; LC transmission lines; link architecture; nanoCMOS technologies; on-chip IO; on-chip communication; on-chip serial links; pre-emphasized differential driver; register-to-register style data transfer; Bandwidth; CMOS process; CMOS technology; Delay; Integrated circuit interconnections; Integrated circuit technology; Network-on-a-chip; Packaging; Power transmission lines; System-on-a-chip;
Conference_Titel :
System-on-Chip, 2006. International Symposium on
Conference_Location :
Tampere
Print_ISBN :
1-4244-0621-8
Electronic_ISBN :
1-4244-0622-6
DOI :
10.1109/ISSOC.2006.322013
