Rapid technology projection for high-level synthesis

Author

Jha, Pradip K. ; Dutt, Nikil D.

Author_Institution

Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA

fYear

1994

Firstpage

155

Lastpage

158

Abstract

High-level synthesis (HLS) tools often use parameterized RT component generators during component selection and allocation. Rapid and accurate technology-specific estimates are therefore crucial for performing effective design space exploration. We describe a fast (on-line) method for estimating the area and delay of regular-structured generic RT components tuned to a particular technology library. The estimation models are generated using a least-square approximation on a set of sample technology data points from selected component implementations. We tested these models against real data points on combinational and sequential components and observed an average error of within 10%. The estimators are integrated with a HLS system to provide on-line technology projection of RT components

Keywords

CMOS integrated circuits; combinatorial circuits; delays; integrated logic circuits; least squares approximations; logic CAD; sequential circuits; CMOS standard cells; area estimation; combinational components; delay estimation; design space exploration; high-level synthesis; least-square approximation; online technology projection; parameterized RT component generators; rapid technology projection; regular-structured generic RT components; sequential components; technology-specific estimates; Computer science; Delay estimation; Equations; Extraterrestrial measurements; High level synthesis; Libraries; Logic design; Space exploration; Space technology; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1994., Proceedings of the Seventh International Conference on

Conference_Location

Calcutta

ISSN

1063-9667

Print_ISBN

0-8186-4990-9

Type

conf

DOI

10.1109/ICVD.1994.282675

Filename

282675