A CAD tool for design of on-chip store and generate scheme

Cellular Automata (CA) and Linear Feed back Shift Register (LFSR) have been proposed for on-chip generation of pseudo-random, pseudo-exhaustive and two-pattern test vectors. The `store and generate´ scheme evolved for on-chip generation of an arbitrary set of deterministic patterns for a combinational logic circuit using LFSR and CA as basic building blocks. In the present work, we report an analytical tool for design of an efficient store and generate scheme keeping both the options of CA and LFSR. Evaluating the given pattern set as a pseudo-noise (PN) sequence, the best possible CA/LFSR is picked up based on the analytical study of characteristic polynomial and phaseshift analysis of various CA/LFSR stages that generate the pattern set with minimal overhead. A CAD (Computer Aided Design) tool has been built around the procedures formulated for this analytical study