Title :
On testability of differential split-level CMOS circuits
Author :
Aziz, S.M. ; Waller, W.A.J.
Author_Institution :
Dept. of Electr. & Electron. Eng., Bangladesh Univ. of Eng. & Technol., Dhaka, Bangladesh
Abstract :
Differential Split-Level (DSL) CMOS logic offers large speed improvement in CMOS circuit techniques. In this paper, the problem of testing DSL circuits is addressed for the first time to the best of our knowledge. The behaviour of DSL circuits under single stuck-at, stuck-on and stuck-open faults is analyzed. It is shown that most of these faults in DSL circuits cannot be deterministically tested by logic monitoring. However, the presence of these faults can be detected by current monitoring
Keywords :
CMOS integrated circuits; circuit analysis computing; integrated logic circuits; logic testing; NAND gate; cascaded chain; circuit testability; current monitoring; deterministic testing; differential split-level CMOS logic; full adder; logic monitoring; single stuck-at faults; stuck-on faults; stuck-open faults; CMOS logic circuits; CMOS technology; Circuit faults; Circuit testing; DSL; Electrical fault detection; Fault detection; Logic circuits; Logic testing; Monitoring;
Conference_Titel :
VLSI Design, 1994., Proceedings of the Seventh International Conference on
Conference_Location :
Calcutta
Print_ISBN :
0-8186-4990-9
DOI :
10.1109/ICVD.1994.282683
