DocumentCode
1714654
Title
Fault-tolerant Routing Approach for Reconfigurable Networks-on-Chip
Author
Rantala, Pekka ; Lehtonen, Teijo ; Isoaho, Jouni ; Plosila, Juha
Author_Institution
Dept. of Inf. Technol., Turku Univ.
fYear
2006
Firstpage
1
Lastpage
4
Abstract
We introduce fault-tolerant on-chip routing philosophy for two-dimensional meshes. It is an extension to the concept of packet connected circuit, PCC. In order to increase reliability we have designed an automatic rerouting property to a single switch node and added return channel to the communication route. An autonomic routing switch node is modeled asynchronously and implemented using Haste language. The logical functionality of routing is illustrated as a single study case in 7*8 mesh. The routing success is further analyzed in congesting and faulty environment
Keywords
fault tolerance; network routing; network-on-chip; 2D meshes; Haste language; PCC; fault tolerant routing; packet connected circuit; reconfigurable network-on-chip; Circuit faults; Communication switching; Fault tolerance; Fault tolerant systems; Integrated circuit interconnections; Network-on-a-chip; Routing; Scalability; Switches; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
System-on-Chip, 2006. International Symposium on
Conference_Location
Tampere
Print_ISBN
1-4244-0621-8
Electronic_ISBN
1-4244-0622-6
Type
conf
DOI
10.1109/ISSOC.2006.321979
Filename
4116467
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