Algorithms for Leakage Reduction with Dual Threshold Design Techniques

The application of devices with different threshold voltages is a state-of-the-art VLSI design technique to reduce the power consumption based on leakage currents. As devices with reduced leakage dissipation have longer delay, the aim of such Dual Threshold CMOS (DTCMOS) approaches is the detection of non-critical gates regarding the circuit´s performance to exchange these with slower but less leaky gates. In our talk, we consider the optimization of DTCMOS circuits, which are modeled as directed acyclic graphs. With each vertex v of a directed acyclic graph, we associate two delay values d₀(v) les d₁ (v) and two leakage values c₀ (v) ges c ₁ (v). The objective is to choose one of the indices 0 or 1 for each vertex, such that the corresponding total delay along any directed path does not exceed the maximum circuit´s delay and that the total leakage is minimized. It is well-known that this problem is NP-hard. We present heuristic approaches to the problem that are based on k-cutsets and k-Sperner families in partially ordered sets