On the synthesis of gate matrix layout

Author

Agarwal, Reena ; Gupta, Indranil Sen

Author_Institution

Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India

fYear

1994

Firstpage

203

Lastpage

206

Abstract

The gate matrix design style has evolved over the last few years as an alternative to semi-custom VLSI design methodology. A new approach for the design of gate matrix layouts from functional specifications is reported in this paper. The method uses genetic algorithms to solve some of the subproblems that arise in the synthesis process. Results obtained by running the algorithm on a number of benchmark circuits have also been reported

Keywords

CMOS integrated circuits; VLSI; circuit layout CAD; genetic algorithms; integrated circuit technology; integrated logic circuits; logic CAD; CMOS IC; VLSI design; design style; functional specifications; gate matrix layout; genetic algorithms; synthesis process; Algorithm design and analysis; CMOS logic circuits; Computer science; Design methodology; Genetic algorithms; Logic design; MOS devices; Space exploration; Strips; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1994., Proceedings of the Seventh International Conference on

Conference_Location

Calcutta

ISSN

1063-9667

Print_ISBN

0-8186-4990-9

Type

conf

DOI

10.1109/ICVD.1994.282685

Filename

282685

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1714717