A methodology for architecture synthesis of cascaded IIR filters on TLU FPGAs

Author

Rathna, G.N. ; Nandy, S.K. ; Parthasarathy, K.

Author_Institution

Dept. of Electr. Eng., Indian Inst. of Sci., Bangalore, India

fYear

1994

Firstpage

225

Lastpage

228

Abstract

In this paper, we propose an architecture synthesis methodology to realize cascaded infinite impulse response (IIR) filter in table look up (TLU) field programmable gate arrays (FPGA). The synthesis procedure involves a systematic transformation of the dependance graph (DG) corresponding to the cascaded IIR filler to a pipelined fixed full size array (PFFSA). We offer an implementation of a cascaded 8th order IIR filters on Xilinx XC3090 FPGA devices

Keywords

VLSI; cascade networks; digital filters; digital signal processing chips; filtering and prediction theory; graph theory; logic arrays; pipeline processing; table lookup; 8th order IIR filters; Xilinx XC3090 FPGA devices; architecture synthesis; cascaded IIR filters; dependance graph; field programmable gate arrays; infinite impulse response; pipelined fixed full size array; systematic transformation; table lookup FPGA; Delay; Digital filters; Digital signal processing; Field programmable gate arrays; Finite impulse response filter; Hardware; IIR filters; Pipeline processing; Transfer functions; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1994., Proceedings of the Seventh International Conference on

Conference_Location

Calcutta

ISSN

1063-9667

Print_ISBN

0-8186-4990-9

Type

conf

DOI

10.1109/ICVD.1994.282690

Filename

282690