Title :
Structural Verification in Minimal Time
Author :
Holzer, M. ; Knerr, B. ; Rupp, M.
Author_Institution :
Inst. for Commun. & RF Eng., Vienna Univ. of Technol., Wien
Abstract :
During the design process of a complex system on chip most time is spent on the verification task. Structural verification is one of the primary strategies for testing. The authors present a method, where the structural testing effort is minimised. This is based on an algorithm, which identifies a set of linearly independent paths of a control flow graph together with a shortest path search. An example is given, where the effort for structural testing can be reduced by more than 40%
Keywords :
flow graphs; formal verification; integrated circuit testing; system-on-chip; control flow graph; path search; structural testing; structural verification; system-on-chip; Circuit testing; Communications technology; Design engineering; Flow graphs; Process design; Radio frequency; Signal processing algorithms; Software testing; System-on-a-chip; Unified modeling language;
Conference_Titel :
System-on-Chip, 2006. International Symposium on
Conference_Location :
Tampere
Print_ISBN :
1-4244-0621-8
Electronic_ISBN :
1-4244-0622-6
DOI :
10.1109/ISSOC.2006.321989
