Detailed routing of multi-terminal nets in FPGAs

We present a multi-terminal routing algorithm for field-programmable gate arrays (FPGAs). The routing problem for the FPGAs is difficult due to the preplaced routing segments that can be connected only by the pre-existing switches. We describe a sequential router that routes multi-terminal nets in a single stage, i.e., global routing is not required. The multi-terminal routing greatly reduces the total wire length as the multi-terminal tree approximates the steiner tree as opposed to a minimum cost spanning tree. Our router requires very small channel width. In addition, our router places an upper bound on the worst case delay by routing a multi-terminal net within its bounding box. Within the bounding box each terminal is routed in a distance that is less than or equal to the max(l(i,o)), where o is an output pin, i is an input pin, and l(i,o) is the Manhattan distance between an input and output pin. Our router has generated excellent routing results for some of the industrial circuits