Title :
An improved CMOS offset-compensated current comparator for high speed applications
Author :
Worapishet, A. ; Hughes, J.B. ; Toumazou, C.
Author_Institution :
Dept. of Electr. Eng., Mahanakorn Univ. of Technol., Bangkok, Thailand
Abstract :
An improved CMOS current comparator suitable for use with either S 2I or S3I switched-current cells is presented in this paper. The circuit also incorporates new design techniques to enhance both speed and resolution. A practical CMOS design is presented and simulations show operation at 80 MHz with 10 bit precision from a 3 V supply
Keywords :
CMOS analogue integrated circuits; analogue-digital conversion; comparators (circuits); compensation; integrated circuit design; switched current circuits; 10 bit; 3 V; 80 MHz; CMOS; S2I switched-current cells; S3I switched-current cells; design techniques; high speed applications; offset-compensated current comparator; precision; resolution; speed; CMOS technology; Calibration; Circuit simulation; Educational institutions; Energy consumption; Laboratories; Medical simulation; Sampling methods; Signal resolution; Voltage;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.704562
