Title :
Architecture for VLSI design of CA based byte error correcting code decoders
Author :
Chowdhury, Dibakar Roy ; Chaudhuri, P. Pal
Author_Institution :
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
Abstract :
This paper reports a novel architecture for byte error correcting code decoders using Cellular Automata (CA). The chip architecture of the basic building blocks for double byte error locating/correcting code (DbEL/DbEC) is presented. Extension of the architecture to detect arbitrary number of byte errors has also been included. The proposed decoder provides a simple, modular, cascadable and cost effective design that is ideally suited for VLSI implementation
Keywords :
VLSI; cascade networks; cellular automata; combinatorial circuits; decoding; error correction codes; error detection codes; integrated logic circuits; VLSI design; byte error correcting code decoders; cellular automata; chip architecture; combinational logic; double byte error locating/correcting code; modular cascadable design; Buildings; Computer architecture; Computer science; Costs; Decoding; Error correction; Error correction codes; Hardware; Reed-Solomon codes; Very large scale integration;
Conference_Titel :
VLSI Design, 1994., Proceedings of the Seventh International Conference on
Conference_Location :
Calcutta
Print_ISBN :
0-8186-4990-9
DOI :
10.1109/ICVD.1994.282703
