Response pipelined CAM chips: the first generation and beyond

Author

Ghose, Kanad ; Dharmaraj, V. Anand

Author_Institution

Dept. of Comput. Sci., State Univ. of New York, Binghamton, NY, USA

fYear

1994

Firstpage

365

Lastpage

368

Abstract

Response-pipelined CAM (RPCAM) chips with W-bit wide words are designed to be cascadable to implement an associative array with a effective word size of K*W bits, where K is a positive integer, and allow a constant search rate of one search per cycle, irrespective of K, without the need for complex wiring or external glue logic. RPCAMs are useful as accelerators for search-intensive applications that use large key sizes. We describe the architecture of the first generation of RPCAMs and an assessment of the 2-micron prototype implementation. We also present an overview of the architecture for the second generation of RPCAMs

Keywords

CMOS integrated circuits; content-addressable storage; integrated memory circuits; pipeline processing; 2-micron prototype; CMOS prototype; accelerators; architecture overview; associative array; cascadable design; content addressable memory; response pipelined CAM chips; search-intensive applications; Acceleration; Associative memory; CADCAM; Computer aided manufacturing; Computer science; Logic arrays; Logic design; Logic devices; Prototypes; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1994., Proceedings of the Seventh International Conference on

Conference_Location

Calcutta

ISSN

1063-9667

Print_ISBN

0-8186-4990-9

Type

conf

DOI

10.1109/ICVD.1994.282720

Filename

282720