A gm/ID based design of high PSR low dropout regulator for SoC applications

Author

Prakash, Gundabathina ; Dhanaraj, K.J.

Author_Institution

Dept. of Electron. & Commun. Eng., Nat. Inst. of Technol. Calicut, Calicut, India

fYear

2015

Firstpage

1

Lastpage

6

Abstract

A design methodology by including the finite PSR of the error amplifier to improve the low frequency PSR of the Low dropout regulator with improved voltage subtractor circuit is proposed. The g_m/I_D method based on exploiting the all regions of operation of the MOS transistor is utilized for the design of LDO regulator. The PSR of the LDO regulator is better than -50dB up to 10MHz frequency for the load currents up to 20mA with 0.15V drop-out voltage. A comparison is made between different schematics of the LDO regulator and proposed methodology for the LDO regulator with improved voltage subtractor circuit. Low frequency PSR of the regulator can be significantly improved with proposed methodology.

Keywords

MOSFET; integrated circuit design; system-on-chip; LDO regulator; MOS transistor; SoC applications; finite power supply rejection; g_m-I_D based design; high PSR low dropout regulator; low frequency improvement; system on chip applications; voltage 0.15 V; voltage subtractor circuit improvement; Design methodology; Logic gates; MOS devices; Regulators; Topology; Transistors; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Communication, Information & Computing Technology (ICCICT), 2015 International Conference on

Conference_Location

Mumbai

Print_ISBN

978-1-4799-5521-3

Type

conf

DOI

10.1109/ICCICT.2015.7045657

Filename

7045657