Investigation of suitable DSP architecture for efficient FPGA implementation of FIR filter

In this paper, we have investigated pipeline and parallel processing architectures of finite impulse response (FIR) filter for efficient field programmable gate array (FPGA) implementation. Our simulation results shows that parallel processing architecture is more efficient as compared to pipeline architecture. Further, it is shown that fast FIR architecture is most suitable as compared to conventional parallel processing architecture due to its hardware complexity reduction. Fast FIR filter architecture shows 25% improvement in area as compared to conventional parallel processing architecture for identical performance.