Title :
Investigation of suitable DSP architecture for efficient FPGA implementation of FIR filter
Author :
Kadam, Mahesh ; Sawarkar, Kishor ; Mande, Sudhakar
Author_Institution :
Dept. of EXTC Eng., Rajiv Gandhi Inst. of Technol., Mumbai, India
Abstract :
In this paper, we have investigated pipeline and parallel processing architectures of finite impulse response (FIR) filter for efficient field programmable gate array (FPGA) implementation. Our simulation results shows that parallel processing architecture is more efficient as compared to pipeline architecture. Further, it is shown that fast FIR architecture is most suitable as compared to conventional parallel processing architecture due to its hardware complexity reduction. Fast FIR filter architecture shows 25% improvement in area as compared to conventional parallel processing architecture for identical performance.
Keywords :
FIR filters; field programmable gate arrays; parallel architectures; pipeline processing; DSP architecture; FIR filter architecture; FPGA implementation; field programmable gate array implementation; finite impulse response filter; hardware complexity reduction; parallel processing architectures; pipeline processing architectures; Computer architecture; Digital signal processing; Field programmable gate arrays; Finite impulse response filters; Hardware; Parallel processing; Throughput; Field Programmable Gate Array (FPGA); Finite impulse response (FIR) filter; MATLAB; System Generator;
Conference_Titel :
Communication, Information & Computing Technology (ICCICT), 2015 International Conference on
Conference_Location :
Mumbai
Print_ISBN :
978-1-4799-5521-3
DOI :
10.1109/ICCICT.2015.7045672