Hardware implementation of lifting based wavelet transform

In this paper, a VLSI implementation of the lifting-based Discrete Wavelet Transform (DWT) is presented. The behavioral description of integer-to-integer CDF (2,2) lifting wavelet, which is used in image compression has been coded in Verilog Hardware Description Language (HDL). The code has been synthesized and then implemented using both Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) design approaches. Post-synthesis and post-layout simulations verify the appropriate operation of he architecture. The resulting hardware can be used in image compression applications such as JPEG2000.