An Approach for In-House USB2.0 Electrical Compliance Testing on Nanoscale SoC

In today´s era SOC manufacturers cannot imagine a product without USB, irrespective of domain i.e. networking automotive, cellular etc. The performance of USB depends fundamentally on the electrical characteristics. USB Implementers Forum (USB-IF) describes the mandatory Electrical compliance tests for certification of USB product. Moreover this gives an extra level of confidence to use the USB product. In legacy method, USB compliance testing is performed on a complete embedded product consisting of software/firmware, controller and USB PHY. In case of any issue or failure, it becomes very hard to isolate the source of problem. That´s why there is need of an approach which can perform compliance testing isolating all the three entity and having sufficient debug capabilities to root cause the issues. This paper explains the reason for opting JTAG based approach for performing all the USB electrical compliance testing prescribed by USB-IF. This approach provides additional debugging capabilities to debug issues at low level.