Design trade-offs in ultra-low-power CMOS and STSCL digital systems

In this article, the main design tradeoffs in design of ultra-low-power (ULP) and robust digital systems will be discussed. Here, the goal is to explore the main tradeoffs among design parameters such as device sizes and supply voltage, and system parameters such as robustness and energy dissipation. This study provides the necessary basis for design optimization and comparing the conventional CMOS topology with more advanced topologies such as subthreshold source-coupled logic (STSCL) topology.