Title :
Design trade-offs in ultra-low-power CMOS and STSCL digital systems
Author :
Tajalli, Armin ; Leblebici, Yusuf
Author_Institution :
Microelectron. Syst. Lab. (LSM), Swiss Fed. Inst. of Technol. (EPFL), Lausanne, Switzerland
Abstract :
In this article, the main design tradeoffs in design of ultra-low-power (ULP) and robust digital systems will be discussed. Here, the goal is to explore the main tradeoffs among design parameters such as device sizes and supply voltage, and system parameters such as robustness and energy dissipation. This study provides the necessary basis for design optimization and comparing the conventional CMOS topology with more advanced topologies such as subthreshold source-coupled logic (STSCL) topology.
Keywords :
CMOS logic circuits; logic design; low-power electronics; STSCL digital systems; conventional CMOS topology; design optimization; design parameters; design trade-off; device sizes; energy dissipation; robust digital systems; subthreshold source-coupled logic topology; supply voltage; system parameters; ultra-low-power CMOS; ultra-low-power systems; CMOS integrated circuits; Delay; Digital systems; Logic gates; Power demand; Power dissipation; Topology;
Conference_Titel :
Circuit Theory and Design (ECCTD), 2011 20th European Conference on
Conference_Location :
Linkoping
Print_ISBN :
978-1-4577-0617-2
Electronic_ISBN :
978-1-4577-0616-5
DOI :
10.1109/ECCTD.2011.6043591
