Synthesis strategies for sub-VT systems

Various synthesis strategies relying on conventional standard-cell libraries (SCLs) are evaluated in order to minimize the energy dissipation per operation in sub-threshold (sub-V_T) systems. First, two sub-V_T analysis methods are reviewed, both of which allow to evaluate the energy dissipation and performance in the sub-V_T regime for designs which have been synthesized using a 65-nm CMOS SCL, characterized at nominal supply voltage. Both analysis methods are able to predict the energy minimum supply voltage (EMV) of any given design. Next, the results of a sub-V_T synthesis at EMV using re-characterized SCLs are compared to the initial synthesis results. Finally, the results of timing-driven synthesis in both the above-V_T and the sub-V_T domain are compared to the results of power-driven synthesis.