VLSI architecture of defect feature extraction based on wavelet packet in ultrasonic nondestructive test

This paper aims at the construction of VLSI architecture of defect extraction based on wavelet packet decomposition. The wavelet packet decomposition for defect feature extraction of ultrasonic signal in nondestructive test is discussed. Based on the features being extracted from decomposed coefficients at different scales and levels, the frame of defect feature extraction is confirmed. The VLSI architectures of wavelet packet decomposition and feature extraction algorithms are configured. The architectures are implemented in FPGA. According to the implementations in FPGAs and experiments to defects classification, the VLSI architecture of defect feature extraction provides a practical and effective solution to real-time embedded reconfigurable ultrasonic signal processing applications.