A 10-bit 5kHz level-crossing ADC

In this paper a 10-bit, 5kHz bandwidth, continuous time ADC, which employs level-crossing sampling to convert an analog signal to a digital one, is presented. The proposed level-crossing ADC does not use any clock and sampling in time is not involved. The level-crossing ADC acquires samples only when they provide a new information about the input signal, thus dissipating power only when needed. Cadence simulation results show that the level-crossing ADC can achieve an SNDR of 71dB over a 5kHz bandwidth. The ADC has been designed in a 150nm CMOS process on a 1.8V supply and its power consumption is activity dependent ranging between 1.3mW with low-activity inputs and 1.74mW with high-activity inputs.