An MDAC architecture with low sensitivity to finite opamp gain

Author

Centurelli, Francesco ; Monsurrò, Pietro ; Trifiletti, Alessandro

Author_Institution

Dipt. di Ing. dell´´Inf., Elettron. e Telecomun., Univ. di Roma La Sapienza, Rome, Italy

fYear

2011

Firstpage

568

Lastpage

571

Abstract

An architecture for MDAC stages with low sensitivity to finite opamp gain is proposed, that allows designing high-precision pipeline ADCs in deep submicron technologies. The standard MDAC architecture is modified by inserting a voltage follower in the feedback path, and zero gain error is achieved if a relationship between the gain of the main opamp and of the opamp used in the voltage follower is satisfied. Simulations using 65-nm CMOS technology are presented to assess the validity of the proposed solution, that allows achieving low sensitivity to finite opamp gain even in case of mismatches in the relationship between the gains of the opamps.

Keywords

CMOS analogue integrated circuits; analogue-digital conversion; digital-analogue conversion; feedback; integrated circuit design; operational amplifiers; CMOS technology; deep submicron technology; feedback path; finite opamp gain; high- precision pipeline ADC design; size 65 nm; standard MDAC architecture; voltage follower insertion; zero gain error; CMOS integrated circuits; CMOS technology; Capacitance; Capacitors; Gain; Logic gates; Pipelines; analog-to-digital converters; pipeline ADC; switched-capacitors;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuit Theory and Design (ECCTD), 2011 20th European Conference on

Conference_Location

Linkoping

Print_ISBN

978-1-4577-0617-2

Electronic_ISBN

978-1-4577-0616-5

Type

conf

DOI

10.1109/ECCTD.2011.6043597

Filename

6043597