A low-power fully differential 9-bit C-2C cyclic ADC

This paper describes a low-power fully differential cyclic ADC. It utilizes a 3-bit C-2C ladder to achieve 9-bit resolution. For the 9-bit resolution the 3-bit C-2C ladder occupies 64 times less area than a binary weighted capacitance array. The operational amplifier with the slew rate detection is used in order to increase the speed of the ADC. The simulated power consumption of the ADC is 33 μW@3.3 V at the sampling rate of 10 kS/s. The DNL and INL are both less than 0.53 LSB. The spurious-free dynamic range (SFDR) is 63 dB and the signal-to-noise and distortion ratio (SNDR) is 54.2 dB. The equivalent number of bits (ENOB) is 8.7.