Title :
Optimization and evaluation of tapered-VTH approach for energy-efficient CMOS buffers
Author :
Frustaci, Fabio ; Corsonello, Pasquale ; Alioto, Massimo
Author_Institution :
Dept. of Electron., Comput. Sci. & Syst., Univ. of Calabria, Rende, Italy
Abstract :
In this paper, the tapered-VTH methodology to design energy-efficient buffers in deep nanometer CMOS technology is deeply analyzed. Its effectiveness is demonstrated under various working conditions (variable final load, activity factor, supply voltage and process corner). Simulations based on a 45-nm technology showed that the tapered-VTH approach can provide a 3X energy reduction, at the parity of the delay, with respect to single-VTH design. This energy reduction was shown to be even greater (up to 4X) in presence of process variations (FF corner).
Keywords :
CMOS digital integrated circuits; buffer circuits; integrated circuit design; delay parity; energy reduction; energy-efficient CMOS buffer design; nanometer CMOS technology; process variations; size 45 nm; tapered threshold voltage approach; CMOS integrated circuits; Delay; Design methodology; Energy consumption; Energy efficiency; Optimization; Threshold voltage;
Conference_Titel :
Circuit Theory and Design (ECCTD), 2011 20th European Conference on
Conference_Location :
Linkoping
Print_ISBN :
978-1-4577-0617-2
Electronic_ISBN :
978-1-4577-0616-5
DOI :
10.1109/ECCTD.2011.6043603
