• DocumentCode
    1717977
  • Title

    Targeting the Motorola RISC compiler for the PowerPC architecture

  • Author

    Shipnes, J.

  • Author_Institution
    Motorola Inc., Austin, TX, USA
  • fYear
    1994
  • Firstpage
    326
  • Lastpage
    331
  • Abstract
    Compiler technology has proven to be an integral part of overall performance in RISC systems. Motorola is providing highly optimizing C and FORTRAN compilers as part of the overall solution for the PowerPC and 88000 RISC architectures. This paper gives an introduction to the Motorola RISC compiler technology and describes how the technology was extended to support the PowerPC architecture in addition to the 88000.<>
  • Keywords
    C language; FORTRAN; program compilers; reduced instruction set computing; C; FORTRAN; Motorola RISC compiler; PowerPC architecture; Assembly systems; Availability; Computer languages; Debugging; Microprocessors; Optimal scheduling; Optimizing compilers; Power generation; Reduced instruction set computing; Tree data structures;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Compcon Spring '94, Digest of Papers.
  • Conference_Location
    San Francisco, CA, USA
  • Print_ISBN
    0-8186-5380-9
  • Type

    conf

  • DOI
    10.1109/CMPCON.1994.282892
  • Filename
    282892
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1717977