DocumentCode
1717994
Title
The PowerPC 603 microprocessor: performance analysis and design trade-offs
Author
Poursepanj, A. ; Ogden, D. ; Burgess, B. ; Gary, S. ; Dietz, C. ; Lee, D. ; Surya, S. ; Peters, M.
Author_Institution
IBM Corp., Austin, TX, USA
fYear
1994
Firstpage
316
Lastpage
323
Abstract
Performance modeling was used in conjunction with application code traces to tune the PowerPC 603 microprocessor design. This modeling technique allowed the design space to be constrained by performance, power and size. Trade-offs were examined with high confidence of final performance. Sampled traces provided a fast turnaround for evaluation of the design space. Finally, simulation model execution of fragments of the traces verified the performance model accuracy.<>
Keywords
IBM computers; microprocessor chips; performance evaluation; PowerPC 603 microprocessor; application code traces; design space constraint; design trade-offs; design tuning; performance analysis; performance model accuracy; simulation model execution; Application software; Character generation; Computational modeling; Delay; Microprocessors; Performance analysis; Reduced instruction set computing; Sampling methods; Scheduling; Workstations;
fLanguage
English
Publisher
ieee
Conference_Titel
Compcon Spring '94, Digest of Papers.
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-8186-5380-9
Type
conf
DOI
10.1109/CMPCON.1994.282893
Filename
282893
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