A New VLSI Implementation of Continuous Wavelet Transform

This paper proposed a VLSI implementation of the continuous wavelet transform. The proposed approach consists of generating a chain of wavelets by multiplying two periodic functions. Each wavelet is then multiplied by the signal to be analyzed, and integrated. And time-frequency decomposition of signal, i.e. partial zoom of the analyzed signal can be gained. The multiplier is a DC-40 GHz INP HBT Gilbert multiplier, and the low-pass filter is a companding log-domain circuit. In the paper first used current-mode companding circuit technology to implement 1D continuous wavelet transform , which has a characteristic of high-speed, expanded frequency, simplified and low-voltage low-power. The PSPICE and Matlab simulation of the reconstruction and the basic cell such as multiplier and LPF are given. The results show that the CWT companding circuit proposed in the article is feasible.