DocumentCode :
1718130
Title :
Estimating the effects of process technology improvements on microprocessor performance
Author :
Barry, M.L.
Author_Institution :
Intergraph Adv. Processor Div., Palo Alto, CA, USA
fYear :
1994
Firstpage :
276
Lastpage :
279
Abstract :
A methodology is presented to estimate the effect of process technology improvements on microprocessor performance. Figures of merit are defined as the ratio of the transistor saturation current divided by the product of the logic voltage swing and the load capacitance. These are determined from a limited set of transistor parameters and layout design rules. Limiting values of the figure of merit are estimated for the cases where the load capacitance is comprised primarily of transistor gates and where the load capacitance is wiring dominated. An intermediate value is then selected based on the design methodology followed historically by the product design group. Good agreement has been found between this simplified technique and more detailed simulations of actual designs.<>
Keywords :
capacitance; circuit layout; microprocessor chips; performance evaluation; semiconductor process modelling; design methodology; figures of merit; layout design rules; limiting values; load capacitance; logic voltage swing; microprocessor performance; process technology improvements; product design group; simulations; transistor gates; transistor saturation current; wiring; Capacitance; Circuits; Design methodology; Logic; Microprocessors; Power supplies; Process design; Transistors; Voltage; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Compcon Spring '94, Digest of Papers.
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-5380-9
Type :
conf
DOI :
10.1109/CMPCON.1994.282897
Filename :
282897
Link To Document :
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