DocumentCode
1718137
Title
Novel hardware architecture of sparse recovery based on FPGAs
Author
Lu, Jicheng ; Zhang, Hao ; Meng, Huadong
Author_Institution
Dept. of Electron. Eng., Tsinghua Univ., Beijing, China
Volume
1
fYear
2010
Abstract
Compressed sensing is currently one of the most popular fields in signal processing, which enables us to acquire “sparse” signals by sampling under Nyquist´s frequency. In this paper, a novel hardware architecture based on Optimized CoSaMP algorithm is presented for sparse recovery of compressed sensing. Due to the crucial calculation of least squares in the algorithm, the proposed architecture develops a least squares module (LS module) with linear array structure, which achieves good efficiency as well as flexibility and scalability. The running results obtained from the implementation on a field-programmable gate array (FPGA) show that our design possesses excellent performance and high accuracy.
Keywords
field programmable gate arrays; image coding; FPGA; Nyquist´s frequency; compressed sensing; hardware architecture; linear array structure; sparse recovery; Algorithm design and analysis; Arrays; Field programmable gate arrays; Hardware; Matching pursuit algorithms; Signal processing algorithms; CoSaMP algorithm; FPGA; compressed sensing; least squares module; sparse recovery;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing Systems (ICSPS), 2010 2nd International Conference on
Conference_Location
Dalian
Print_ISBN
978-1-4244-6892-8
Electronic_ISBN
978-1-4244-6893-5
Type
conf
DOI
10.1109/ICSPS.2010.5555628
Filename
5555628
Link To Document