A SAT Method for Improving Test Pattern Generation

This paper presents a solution for test pattern generation (TPG) based on Boolean satisfiability (SAT). The key to a SAT-solver can be scalable is that it is able to take into account the information about high-level structure of formulas. The paper augments a circuit structure layer to the SAT-solver to maintain circuit-related information and value justification relations. It dovetails binary decision graphs (BDD) and SAT techniques to improve the efficiency of test pattern generation. More specifically, it first exploits inexpensive reconvergent fanout analysis of circuit to gather information on the local signal correlation by using BDD learning. It then uses the above learned information to restrict and focus the overall search space of SAT-based TPG. Its learning technique is effective and lightweight. The experimental results demonstrate the effectiveness of the approach.