Title :
The POWER2 processor
Author :
Barreh, J. ; Dhawan, S. ; Hicks, T. ; Shippy, D.
Author_Institution :
IBM Corp., Austin, TX, USA
Abstract :
The IBM POWER2 is a second-generation, multi-chip superscalar RISC processor. It provides dual branch processing units, dual fixed-point units, dual floating-point units, and advanced superscalar techniques. It is capable of executing 6 instructions per cycle and 8 operations per cycle. The processor also provides large caches, long cache lines, and high bandwidth buses to memory and I/O.<>
Keywords :
IBM computers; buffer storage; digital arithmetic; microprocessor chips; multiprocessing systems; reduced instruction set computing; system buses; IBM POWER2 processor; cache lines; dual branch processing units; dual fixed-point units; dual floating-point units; high bandwidth I/O bus; high bandwidth memory bus; multi-chip superscalar RISC processor; Bandwidth; Cache storage; Decoding; Electrostatic precipitators; Inspection; Logic; Maintenance engineering; Prefetching; Reduced instruction set computing; Registers;
Conference_Titel :
Compcon Spring '94, Digest of Papers.
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-5380-9
DOI :
10.1109/CMPCON.1994.282901
