Low error bit width reduction for structural adders of FIR filters

The optimization of fixed coefficient FIR filter implementation has been focused mainly on the multiplier block where full precision fixed point arithmetic is normally used. Recently, an optimization method was proposed for the structural adders in FIR filters. This paper further proposes a method for gradually reducing the number of fractional bits within the structural adder block such that the output has the same number of fractional bits as the input signal. The resulting output signal is very close to the rounded signal obtained from full-precision calculation. This is achieved by applying truncation and round-half-up operations on the inputs to the structural adders. The proposed method reduces the area of FIR filter implementation and the magnitude of the error is not larger than one LSB. Example filters were synthesized and the simulation results show an error mean of less than 0.25% of the LSB and a variance of less than 15% of the LSB. Overall, the areas of the example filters have been reduced by up to 12.42%.