DocumentCode :
1718532
Title :
A design approach for networks of Self-Sampled All-Digital Phase-Locked Loops
Author :
Akre, J.M. ; Juillard, J. ; Javidan, M. ; Zianbetov, E. ; Galayko, D. ; Korniienko, A. ; Colinet, E.
Author_Institution :
SUPELEC, Gif-sur-Yvette, France
fYear :
2011
Firstpage :
725
Lastpage :
728
Abstract :
This paper addresses the problem of the stability and the performance analysis of N-nodes cartesian networks of self-sampled all digital phase-locked loops. It can be demonstrated that under certain conditions (such as proper filter coefficient values), a global and a local synchronization can be obtained. Our approach to find the optimal conditions consists of analyzing a corresponding linear average system of the cartesian network rather than constructing a piecewise-linear system which is extremely difficult to analyse. The constructed corresponding system takes into account the non-linearity of the network and especially the self-sampling property. It is then analyzed by linear performance criteria such as modulus margin to guarantee a robust stability of the cartesian network. The reliability of our approach is proved by transient simulations in networks of different sizes.
Keywords :
circuit reliability; circuit stability; digital phase locked loops; synchronisation; N-nodes cartesian networks; linear average system; linear performance criteria; local synchronization; modulus margin; network design approach; piecewise-linear system; self-sampled all-digital phase-locked loops; Clocks; Numerical stability; Phase frequency detector; Power system stability; Stability criteria; Synchronization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuit Theory and Design (ECCTD), 2011 20th European Conference on
Conference_Location :
Linkoping
Print_ISBN :
978-1-4577-0617-2
Electronic_ISBN :
978-1-4577-0616-5
Type :
conf
DOI :
10.1109/ECCTD.2011.6043646
Filename :
6043646
Link To Document :
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