High performance parallelised 3GPP turbo decoder

The maximum a-posteriori based turbo decoder is extremely complex due to the large number of identical operations repeated to sequence for the processing of huge data volume. This also introduces a significant decoding delay which is undesirable for real-time applications as required in the 3G communication systems. However, this scenario shows that the algorithm is highly parallelisable. We propose a parallelised max-log-MAP (P-max-log-MAP) model which exploits the sub-word parallelism (SWP) and very long instruction word (VLIW) architecture of a microprocessor or a DSP. The proposed model reduces considerably the complexity of max-log-MAP algorithm wherein it maximises the decoding performance of 3GPP turbo codes; therefore facilitates easy implementation. The proposed model is implemented on the Analog Devices TigerSHARC dual-core DSP. Based on this dual-cores DSP, we also propose a parallel sliding window (P-SW) scheme where two P-max-Log-MAP component decoders are able to work in parallel for the processing of two sliding windows. We show that the turbo decoder uses the P-max-log-MAP combined with the P-SW to achieve decoding throughput exceeding 2 Mbps on a single chip DSP implementation.