A high-speed ACS design based on 4:2 compression array

Add - Compare - Select (ACS) unit forms the kernel of Viterbi decoder. High speed ACS unit design for convolutional codes is the research focus at high data rate communication applications. In this paper, we proposed a high-speed ACS architecture based on 4:2 compression arrays. By using 4:2 compressors, the compare operations are concurrent with add operations in ACS unit. With the proposed concurrent architecture, it can predominantly decrease the timing delay of the critical path of ACS. In order to validate the feasibility of the proposed method, we implemented it on radix-4 ACS unit with 32 bit width operands. Compared with the traditional method, the experiment data shows a worst-case delay reduction of better than 50% at 0.25-micron CMOS processes.