Advanced modulation scheme for three-phase three-switch buck-type PWM rectifier preventing mains current distortion originating from sliding input filter capacitor voltage intersections

Modulation schemes for three-phase three-switch buck-type PWM rectifiers where the switching state of one bridge leg is clamped within a Π/3-wide interval of the mains period do guarantee minimum switching losses as well as minimum input filter capacitor voltage ripple and minimum DC current ripple. However, as shown in this paper by a detailed analysis of the time behavior of the input filter capacitor voltages within a pulse period such modulation schemes are characterized by the occurrence of sliding intersections of the filter capacitor voltages which do cause input current distortion. An advanced modulation scheme is proposed which does prevent the input current distortion and does allow to maintain the optimum performance of conventional modulation schemes.