A PA-RISC microprocessor PA/50L for low-cost systems

Author

Okada, T. ; Narita, S. ; Nishii, O. ; Hiratsuka, N. ; Hayashi, N. ; Asai, M. ; Fujiwara, S. ; Satoh, M. ; Nishimoto, J. ; Aoki, H. ; Uchiyama, K. ; Matsuo, S. ; Takewa, H. ; Yamada, K. ; Kainaga, M. ; Nakagawa, N. ; Yamagami, M. ; Takeda, H. ; Funabashi,

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo, Japan

fYear

1994

Firstpage

47

Lastpage

52

Abstract

The PA/50L is a low-cost, low-power microprocessor from Hitachi Ltd. that is fully compatible with the PA-RISC architecture 1.1, third edition. This microprocessor achieves 55 VAX MIPS (Dhrystone 1.1), 10.6 MFLOPS (LINPACK inner loop) and 1.3 W at 33 MHz. In order to achieve high performance with no external cache, a non-blocking cache and a data prefetch instruction are provided. This paper gives an overview of the microprocessor and describes its capabilities.<>

Keywords

buffer storage; microprocessor chips; performance evaluation; reduced instruction set computing; 1.3 W; 10.6 MFLOPS; 33 MHz; 55 MIPS; Dhrystone 1.1; Hitachi PA/50L microprocessor; LINPACK inner loop; PA-RISC architecture 1.1, third edition; data prefetch instruction; high performance; low-cost systems; nonblocking cache; Clocks; Costs; Decoding; Microprocessors; Pipelines; Power supplies; Prefetching; Registers; SDRAM; Signal design;

fLanguage

English

Publisher

ieee

Conference_Titel

Compcon Spring '94, Digest of Papers.

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-8186-5380-9

Type

conf

DOI

10.1109/CMPCON.1994.282946

Filename

282946