Architectural coefficient synthesis for the implementation of optimal higher-order ΔΣ analog-to-digital converters

This paper describes a method to synthesize architectural coefficients for higher-order ΔΣ modulators. Considerations for maximum dynamic range and optimal power are addressed. First, a modulator with optimal theoretical performance is synthesized. Then, the theoretical ΔΣ ADC is scaled to make it realizable with maximum dynamic range, and finally, the modulator is further modified for optimal power and area performance. During each of the steps, the modulator theoretical performance and stability characteristics are preserved. Construction of an optimal seventh-order modulator is demonstrated. It is also shown that the coefficient synthesis significantly affects the power and area consumption