• DocumentCode
    1720597
  • Title

    Determination of junction depths for phosphorous diffused in silicon

  • Author

    French, C.S. ; Belman, D.P. ; Kardes, D.E. ; Hendricks, R.W.

  • Author_Institution
    Dept. of Mater. Sci. & Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
  • fYear
    2001
  • fDate
    6/23/1905 12:00:00 AM
  • Firstpage
    51
  • Lastpage
    59
  • Abstract
    P was diffused into p-type Si wafers containing B at 1100°C for six different times using a solid state source and a standard pre-deposition process. Secondary ion mass spectrometry (SIMS) provided profiles of dopant concentration versus wafer depth from which both the surface concentration and the junction depths for the six wafers were determined. These profiles were fitted acceptably well by the constant supply model of diffusion in the dilute “tail region” identified by Fair, although indications of concentration-dependent diffusion were observed. Two independent determinations of the sheet resistivity of each sample were made. The results confirmed the correct operation of our custom-built sheet resistivity system. The resulting data allow us to predict the junction depth within 0.2 μm over a range from 1.0 to 2.0 μm. A plot of the dopant surface concentration, N0, versus the product of the sheet resistivity and the junction depth, Rsxj, agrees well with data from the Irvin plot
  • Keywords
    diffusion; doping profiles; electrical resistivity; elemental semiconductors; heat treatment; phosphorus; secondary ion mass spectra; semiconductor doping; semiconductor process modelling; silicon; 1 to 2 micron; 1100 C; B doping; Irvin plot; P diffusion; SIMS; Si:B; Si:B,P; concentration-dependent diffusion; constant supply diffusion model; dilute tail region; dopant concentration profiles; dopant surface concentration; junction depth prediction; junction depths; p-type Si wafers; phosphorous diffusion; secondary ion mass spectrometry; sheet resistivity; sheet resistivity system; silicon; solid state source; standard pre-deposition process; surface concentration; wafer depth; Conductivity; Fabrication; Laboratories; Mass spectroscopy; Materials science and technology; Optical microscopy; Probes; Semiconductor device testing; Silicon; Solid state circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    University/Government/Industry Microelectronics Symposium, 2001. Proceedings of the Fourteenth Biennial
  • Conference_Location
    Richmond, VA
  • ISSN
    0749-6877
  • Print_ISBN
    0-7803-6691-3
  • Type

    conf

  • DOI
    10.1109/UGIM.2001.960293
  • Filename
    960293