Centralized power gating technique for embedded systems

Embedded systems need to save as much energy as possible in order to prolong the battery life. Many applications only require the use of the system for a brief period of time followed by a long stand-by phase. Static currents in digital systems can drag large amounts of charge, particularly at high temperatures. Power gating has been used to reduce the impact of these currents but it is difficult to include it in the digital design flow. This paper presents a method of implementing power gating that does not require special digital cells, it is easy to size and includes soft start and monitor functions.