A two stages MMIC CDMA power amplifier using harmonic load pull simulation technique

Author

Cao, Jiang ; Singh, Rajinder ; Liang, Bo ; Wang, Xlnwei ; Sze, Khoo Ee ; Nakamura, Hiroshl

Author_Institution

Inst. of Microelectron., Singapore

Volume

2

fYear

1999

fDate

11/1/1999 12:00:00 AM

Firstpage

437

Abstract

This paper reports a two stages MMIC power amplifier with low quiescent current and high power added efficiency (PAE) for PCS CDMA application. Based on an accurate large signal PHEMT model, a systematic load (source) pull simulation scheme was developed to design the linear power amplifier. The two stages PCS CDMA PA attained over 40% PAE, 28.5 dBm output power and 18.5 dB gain at -45 dBc adjacent channel power rejection (ACPR) under a supply voltage of 3.6 V. The total quiescent current is only 110 mA. The chip size of the amplifier is 0.86×1.24 mm and assembled in 16 pins HS-SSOP plastic package

Keywords

HEMT integrated circuits; MMIC power amplifiers; code division multiple access; 110 mA; 18.5 dB; 3.6 V; 40 percent; PCS CDMA; adjacent channel power rejection; harmonic load pull simulation; large-signal model; power added efficiency; quiescent current; two-stage PHEMT MMIC power amplifier; wireless communication; High power amplifiers; Load modeling; MMICs; Multiaccess communication; PHEMTs; Personal communication networks; Power amplifiers; Power system harmonics; Power system modeling; Signal design;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference, 1999 Asia Pacific

Print_ISBN

0-7803-5761-2

Type

conf

DOI

10.1109/APMC.1999.829899

Filename

829899