VLSI timing simulation with selective dynamic regionization

Accurate timing simulations are crucial to the design of MOS VLSI circuits, but can take prohibitively large amounts of time on a typical engineering workstation. This paper describes dynamic regionization techniques to an event-based simulator for MOS timing simulation that has proven to be more efficient than, and as accurate as, the static regionization method. The MOS network is first statically partitioned into groups of strongly coupled nodes called regions. Big regions are then incrementally and dynamically partitioned into and replaced by subregions. Subregions are treated just like normal regions in the event-based simulation process. This simulator has been used to verify the timing and functionality of several large VLSI chips. Performance is 2.5 to 7 times faster than a static regionization method